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| PRELIMINARY AM29F040B 4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory Distinctive Characteristics s 5.0 V 10% for read and write operations -- Minimizes system level power requirements s Manufactured on 0.35 m process technology -- Compatible with 0.5 m Am29F040 device s High performance -- Access times as fast as 55 ns s Low power consumption -- 20 mA typical active read current -- 30 mA typical program/erase current -- 1 A typical standby current (standard access time to active mode) s Flexible sector architecture -- 8 uniform sectors of 64 Kbytes each -- Any combination of sectors can be erased -- Supports full chip erase -- Sector protection: A hardware method of locking sectors to prevent any program or erase operations within that sector s Embedded Algorithms -- Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors -- Embedded Program algorithm automatically writes and verifies bytes at specified addresses s Minimum 1,000,000 program/erase cycles per sector guaranteed s Package options -- 32-pin PLCC, TSOP, or PDIP s Compatible with JEDEC standards -- Pinout and software compatible with single-power-supply Flash standard -- Superior inadvertent write protection s Data# Polling and toggle bits -- Provides a software method of detecting program or erase cycle completion s Erase Suspend/Erase Resume -- Suspends a sector erase operation to read data from, or program data to, a non-erasing sector, then resumes the erase operation Publication# 21445 Rev: B Amendment/+2 Issue Date: April 1998 PRELIMINARY GENERAL DESCRIPTION The AM29F040B is a 4 Mbit, 5.0 volt-only Flash memory organized as 524,288 Kbytes of 8 bits each. The 512 Kbytes of data are divided into eight sectors of 64 Kbytes each for flexible erase capability. The 8 bits of data appear on DQ0-DQ7. The AM29F040B is offered in 32-pin PLCC, TSOP, and PDIP packages. This device is designed to be programmed in-system with the standard system 5.0 volt VCC supply. A 12.0 volt VPP is not required for write or erase operations. The device can also be programmed in standard EPROM programmers. This device is manufactured using AMD's 0.35 m process technology, and offers all the features and benefits of the Am29F040, which was manufactured using 0 . 5 m p r o c e s s t e c h n o l o g y. I n a d d t i o n , t h e AM29F040B has a second toggle bit, DQ2, and also offers the ability to program in the Erase Suspend mode. The standard AM29F040B offers access times of 55, 70, 90, 120, and 150 ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single 5.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm--an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm--an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The system can place the device into the standby mode. Power consumption is greatly reduced in this mode. AMD's Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection. 2 AM29F040B PRELIMINARY PRODUCT SELECTOR GUIDE Family Part Number Speed Option VCC = 5.0 V 5% VCC = 5.0 V 10% 55 55 25 -55 -70 70 70 30 -90 90 90 35 -120 120 120 50 -150 150 150 55 AM29F040B Max access time, ns (tACC) Max CE# access time, ns (tCE) Max OE# access time, ns (tOE) Note: See the "AC Characteristics" section for more information. BLOCK DIAGRAM DQ0-DQ7 VCC VSS Erase Voltage Generator Input/Output Buffers WE# State Control Command Register PGM Voltage Generator Chip Enable Output Enable Logic STB Data Latch CE# OE# STB VCC Detector Timer Address Latch Y-Decoder Y-Gating X-Decoder Cell Matrix A0-A18 21445B-1 AM29F040B 3 PRELIMINARY CONNECTION DIAGRAMS A18 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PDIP 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE# VCC A12 A15 A16 A18 A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 21445B-2 4 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 PLCC 14 15 16 17 18 19 20 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 VSS A17 WE# 21445B-3 A11 A9 A8 A13 A14 A17 WE# VCC A18 A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-Pin Standard TSOP 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-Pin Reverse TSOP 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A11 A9 A8 A13 A14 A17 WE# VCC A18 A16 A15 A12 A7 A6 A5 A4 21445B-4 4 AM29F040B PRELIMINARY PIN CONFIGURATION A0-A18 = Address Inputs Data Input/Output Chip Enable Write Enable Output Enable Device Ground DQ0-DQ7 = CE# WE# OE# VSS VCC = = = = LOGIC SYMBOL 19 A0-A18 DQ0-DQ7 CE# OE# WE# 8 = +5.0 V single power supply (see Product Selector Guide for device speed ratings and voltage supply tolerances) 21445B-5 ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: AM29F040B -55 E C B OPTIONAL PROCESSING Blank = Standard Processing B = Burn-in (Contact an AMD representative for more information) TEMPERATURE RANGE C= Commercial (0C to +70C) I = Industrial (-40C to +85C) E= Extended (-55C to +125C) PACKAGE TYPE P = 32-Pin Plastic DIP (PD 032) J = 32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032) E = 32-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 032) F = 32-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR032) SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER/DESCRIPTION AM29F040B 4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only Sector Erase Flash Memory 5.0 V Read, Program, and Erase Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Valid Combinations AM29F040B-55 JC, JI, JE, EC, EI, EE, FC, FI, FE AM29F040B-70 AM29F040B-90 AM29F040B-120 AM29F040B-150 PC, PI, PE, JC, JI, JE, EC, EI, EE, FC, FI, FE AM29F040B 5 PRELIMINARY DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data informa- tion needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The appropriate device bus operations table lists the inputs and control levels required, and the resulting output. The following subsections describe each of these operations in further detail. Table 1. AM29F040B Device Bus Operations Operation Read Write CMOS Standby TTL Standby Output Disable CE# L L VCC 0.5 V H L OE# L H X X H WE# H L X X H A0-A20 AIN AIN X X X DQ0-DQ7 DOUT DIN High-Z High-Z High-Z Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 0.5 V, X = Don't Care, DIN = Data In, DOUT = Data Out, AIN = Address In Note: See the section on Sector Protection for more information. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See "Reading Array Data" for more information. Refer to the AC Read Operations table for timing specifications and to the Read Operations Timings diagram for the timing waveforms. ICC1 in the DC Characteristics table represents the active current specification for reading array data. dicate the address space that each sector occupies. A "sector address" consists of the address bits required to uniquely select a sector. See the "Command Definitions" section for details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7-DQ0. Standard read cycle timings apply in this mode. Refer to the "Autoselect Mode" and "Autoselect Command Sequence" sections for more information. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC Characteristics" section contains timing specification tables and timing diagrams for write operations. Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7-DQ0. Standard read cycle timings and ICC read specifications apply. Refer to "Write Operation Status" for more information, and to each AC Characteristics section for timing diagrams. Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. An erase operation can erase one sector, multiple sectors, or the entire device. The Sector Address Tables in- Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. 6 AM29F040B PRELIMINARY The device enters the CMOS standby mode when the CE# pin is held at VCC 0.5 V. (Note that this is a more restricted voltage range than VIH.) The device enters the TTL standby mode when CE# is held at VIH. The device requires the standard access time (tCE) before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 in the DC Characteristics tables represents the standby current specification. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state. Table 2. Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 A18 0 0 0 0 1 1 1 1 Sector Addresses Table A16 0 1 0 1 0 1 0 1 Address Range 00000h-0FFFFh 10000h-1FFFFh 20000h-2FFFFh 30000h-3FFFFh 40000h-4FFFFh 50000h-5FFFFh 60000h-6FFFFh 70000h-7FFFFh A17 0 0 1 1 0 0 1 1 Note: All sectors are 64 Kbytes in size. Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7-DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes (High Voltage Method) table. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The Command Definitions table shows the remaining address bits that are don't care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7-DQ0. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in the Command Definitions table. This method does not require VID. See "Command Definitions" for details on using the autoselect mode. AM29F040B 7 PRELIMINARY Table 3. Description Manufacturer ID: AMD Device ID: AM29F040B Sector Protection Verification AM29F040B Autoselect Codes (High Voltage Method) A15-A10 X X X A9 VID VID VID A8-A7 X X X A6 VIL VIL VIL A5-A2 X X X A1 VIL VIL VIH A0 VIL VIH VIL Identifier Code on DQ7-DQ0 01h A4h 01h (protected) 00h (unprotected) A18-A16 X X Sector Address Sector Protection/Unprotection The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection/unprotection must be implemented using programming equipment. The procedure requires a high voltage (VID) on address pin A9 and the control pins. Details on this method are provided in a supplement, publication number 19957. Contact an AMD representative to obtain a copy of the appropriate document. The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at its factory prior to shipping the device through AMD's ExpressFlashTM Service. Contact an AMD representative for details. It is possible to determine whether a sector is protected or unprotected. See "Autoselect Mode" for details. gramming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO. Write Pulse "Glitch" Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up. Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to the Command Definitions table). In addition, the following hardware data protection measures prevent accidental erasure or pro- COMMAND DEFINITIONS Writing specific address and data commands or sequences into the command register initiates device operations. The Command Definitions table defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the "AC Characteristics" section. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erasesuspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array 8 AM29F040B PRELIMINARY data with the same exception. See "Erase Suspend/ Erase Resume Commands" for more information on this mode. The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the "Reset Command" section, next. See also "Requirements for Reading Array Data" in the "Device Bus Operations" section for more information. The Read Operations table provides the read parameters, and Read Operation Timings diagram shows the timing diagram. Method) table, which is intended for PROM programmers and requires VID on address bit A9. The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h or retrieves the manufacturer code. A read cycle at address XX01h returns the device code. A read cycle containing a sector address (SA) and the address 02h in returns 01h if that sector is protected, or 00h if it is unprotected. Refer to the Sector Address tables for valid sector addresses. The system must write the reset command to exit the autoselect mode and return to reading array data. Reset Command Writing the reset command to the device resets the device to reading array data. Address bits are don't care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend). Byte Program Command Sequence Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verify the programmed cell margin. The Command Definitions take shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7 or DQ6. See "Write Operation Status" for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a "0" back to a "1". Attempting to do so may halt the operation and set DQ5 to "1", or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still "0". Only erase operations can convert a "0" to a "1". Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. The Command Definitions table shows the address and data requirements. This method is an alternative to that shown in the Autoselect Codes (High Voltage AM29F040B 9 PRELIMINARY plete, the device returns to reading array data and addresses are no longer latched. START Write Program Command Sequence Figure 2 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in "AC Characteristics" for parameters, and to the Chip/Sector Erase Operation Timings for timing waveforms. Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. The Command Definitions table shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 s begins. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 s, otherwise the last address and command might not be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50 s, the system need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to reading array data. The system must rewrite the command sequence and any additional sector addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out. (See the "DQ3: Sector Erase Timer" section.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. Refer to "Write Operation Status" for information on these status bits. Embedded Program algorithm in progress Data Poll from System Verify Data? No Yes No Increment Address Last Address? Yes Programming Completed 21445B-6 Note: See the appropriate Command Definitions table for program command sequence. Figure 1. Program Operation Chip Erase Command Sequence Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. The Command Definitions table shows the address and data requirements for the chip erase command sequence. Any commands written to the chip during the Embedded Erase algorithm are ignored. The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See "Write Operation Status" for information on these status bits. When the Embedded Erase algorithm is com- 10 AM29F040B PRELIMINARY Figure 2 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the "AC Characteristics" section for parameters, and to the Sector Erase Operations Timing diagram for timing waveforms. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See "Autoselect Command Sequence" for more information. The system must write the Erase Resume command (address bits are "don't care") to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing. Erase Suspend/Erase Resume Commands The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out period and suspends the erase operation. Addresses are "don't-cares" when writing the Erase Suspend command. When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (The device "erase suspends" all sectors selected for erasure.) Normal read and write timings and command definitions apply. Reading at any address within erase-suspended sectors produces status data on DQ7-DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See "Write Operation Status" for information on these status bits. After an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See "Write Operation Status" for more information. START Write Erase Command Sequence Data Poll from System Embedded Erase algorithm in progress No Data = FFh? Yes Erasure Completed 21445B-7 Notes: 1. See the appropriate Command Definitions table for erase command sequence. 2. See "DQ3: Sector Erase Timer" for more information. Figure 2. Erase Operation AM29F040B 11 PRELIMINARY Table 4. Cycles AM29F040B Command Definitions Bus Cycles (Notes 2-4) Command Sequence (Note 1) Read (Note 5) Reset (Note 6) Manufacturer ID First Addr RA XXX 555 555 555 555 555 555 XXX XXX Data RD F0 AA AA AA AA AA AA B0 30 Second Addr Data Third Addr Fourth Data Addr Data Fifth Addr Data Sixth Addr Data 1 1 4 4 4 4 6 6 1 1 2AA 2AA 2AA 2AA 2AA 2AA 55 55 55 55 55 55 555 555 555 555 555 555 90 90 90 A0 80 80 X00 X01 SA X02 PA 555 555 01 A4 XX00 XX01 PD AA AA 2AA 2AA 55 55 555 SA 10 30 Autoselect Device ID (Note 7) Sector Protect Verify (Note 8) Program Chip Erase Sector Erase Erase Suspend (Note 9) Erase Resume (Note 10) Legend: X = Don't care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A18-A16 select a unique sector. Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Except when reading array or autoselect data, all bus cycles are write operations. 4. Address bits A18-A11 are don't cares for unlock and command cycles, unless SA or PA required. 5. No unlock or command cycles required when reading array data. 6. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status data). 7. The fourth cycle of the autoselect command sequence is a read cycle. 8. The data is 00h for an unprotected sector and 01h for a protected sector. See "Autoselect Command Sequence" for more information. 9. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 10. The Erase Resume command is valid only during the Erase Suspend mode. 12 AM29F040B PRELIMINARY WRITE OPERATION STATUS The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 5 and the following subsections describe the functions of these bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first. rithms) figure in the "AC Characteristics" section illustrates this. Table 5 shows the outputs for Data# Polling on DQ7. Figure 3 shows the Data# Polling algorithm. DQ7: Data# Polling The Data# Polling bit, DQ7, indicates to the host sys tem whether an Embedded Algor ithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the program or erase command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 2 s, then the device returns to reading array data. During the Embedded Erase algorithm, Data# Polling produces a "0" on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a "1" on DQ7. This is analogous to the complement/true datum output described for the Embedded Program algorithm: the erase function changes all the bits in a sector to "1"; prior to this, the device outputs the "complement," or "0." The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 s, then the device returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ7-DQ0 on the following read cycles. This is bec a us e D Q 7 m ay c ha ng e as y n c hr on ou sly w it h DQ0-DQ6 while Output Enable (OE#) is asserted low. The Data# Polling Timings (During Embedded Algo- START Read DQ7-DQ0 Addr = VA DQ7 = Data? Yes No No DQ5 = 1? Yes Read DQ7-DQ0 Addr = VA DQ7 = Data? Yes No FAIL PASS Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = "1" because DQ7 may change simultaneously with DQ5. 21445B-8 Figure 3. Data# Polling Algorithm AM29F040B 13 PRELIMINARY DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. (The system may use either OE# or CE# to control the read cycles.) When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 s, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erasesuspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on "DQ7: Data# Polling"). If a program address falls within a protected sector, DQ6 toggles for approximately 2 s after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. The Write Operation Status table shows the outputs for Toggle Bit I on DQ6. Refer to Figure 4 for the toggle bit algorithm, and to the Toggle Bit Timings figure in the "AC Characteristics" section for the timing diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on "DQ2: Toggle Bit II". sure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 5 to compare outputs for DQ2 and DQ6. Figure 4 shows the toggle bit algorithm in flowchart form, and the section "DQ2: Toggle Bit II" explains the algorithm. See also the "DQ6: Toggle Bit I" subsection. Refer to the Toggle Bit Timings figure for the toggle bit timing diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Figure 4 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7-DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 4). DQ2: Toggle Bit II The "Toggle Bit II" on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for era- DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a "1." This is a failure condition that indicates the program or erase cycle was not successfully completed. 14 AM29F040B PRELIMINARY The DQ5 failure condition may appear if the system tries to program a "1" to a location that is previously programmed to "0." Only an erase operation can change a "0" back to a "1." Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a "1." Under both these conditions, the system must issue the reset command to return the device to reading array data. START Read DQ7-DQ0 DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire timeout also applies after each additional sector erase command. When the time-out is complete, DQ3 switches from "0" to "1." The system may ignore DQ3 if the system can guarantee that the time between additional sector erase commands will always be less than 50 s. See also the "Sector Erase Command Sequence" section. After the sector erase command sequence is written, the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure the device has accepted the command sequence, and then read DQ3. If DQ3 is "1", the internally controlled erase cycle has begun; all further commands (other than Erase Suspend) are ignored until the erase operation is complete. If DQ3 is "0", the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 5 shows the outputs for DQ3. Read DQ7-DQ0 Note 1 Toggle Bit = Toggle? Yes No No DQ5 = 1? Yes Read DQ7-DQ0 Twice (Notes 1, 2) Toggle Bit = Toggle? No Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete Notes: 1. Read toggle bit twice to determine whether or not it is toggling. See text. 2. Recheck toggle bit because it may stop toggling as DQ5 changes to "1". See text. 21445B-9 Figure 4. Toggle Bit Algorithm AM29F040B 15 PRELIMINARY Table 5. Operation Standard Mode Erase Suspend Mode Embedded Program Algorithm Embedded Erase Algorithm Reading within Erase Suspended Sector Reading within Non-Erase Suspended Sector Erase-Suspend-Program Write Operation Status DQ7 (Note 1) DQ7# 0 1 Data DQ7# DQ6 Toggle Toggle No toggle Data Toggle DQ5 (Note 2) 0 0 0 Data 0 DQ3 N/A 1 N/A Data N/A DQ2 (Note 1) No toggle Toggle Toggle Data N/A Notes: 1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 2. DQ5 switches to `1' when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See "DQ5: Exceeded Timing Limits" for more information. 16 AM29F040B PRELIMINARY ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . -65C to +125C Ambient Temperature with Power Applied. . . . . . . . . . . . . . -55C to +125C Voltage with Respect to Ground VCC (Note 1) . . . . . . . . . . . . . . . . . -2.0 V to 7.0 V A9, OE# (Note 2) . . . . . . . . . . . . . -2.0 V to 12.5 V All other pins (Note 1) . . . . . . . . . . -2.0 V to 7.0 V Output Short Circuit Current (Note 3) . . . . . . 200 mA Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, inputs may undershoot VSS to -2.0 V for periods of up to 20 ns. See Figure 5. Maximum DC voltage on input and I/O pins is V CC + 0.5 V. During voltage transitions, input and I/O pins may overshoot to VCC + 2.0 V for periods up to 20 ns. See Figure 6. 2. Minimum DC input voltage on A9 pin is -0.5 V. During voltage transitions, A9 and OE# may undershoot VSS to -2.0 V for periods of up to 20 ns. See Figure 5. Maximum DC input voltage on A9 and OE# is 12.5 V which may overshoot to 13.5 V for periods up to 20 ns. 3. No more than one output shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. -2.0 V 20 ns 21445B-10 20 ns +0.8 V -0.5 V 20 ns Figure 5. Maximum Negative Overshoot Waveform 20 ns VCC +2.0 V VCC +0.5 V 2.0 V 20 ns 20 ns 21445B-11 Figure 6. Maximum Positive Overshoot Waveform OPERATING RANGES Commer cial (C) Devices Ambient Temperature (TA) . . . . . . . . . . . 0C to +70C Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . -40C to +85C Extended (E) Devices Ambient Temperature (TA) . . . . . . . . -55C to +125C VCC Supply Voltages VCC for 5% devices . . . . . . . . . . .+4.75 V to +5.25 V VCC for 10% devices . . . . . . . . . . . .+4.5 V to +5.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. AM29F040B 17 PRELIMINARY DC CHARACTERISTICS TTL/NMOS Compatible Parameter Symbol ILI ILIT ILO ICC1 ICC2 ICC3 VIL VIH VID VOL VOH VLKO Parameter Description Input Load Current A9 Input Load Current Output Leakage Current VCC Active Read Current (Note 1) VCC Active Write (Program/Erase) Current (Notes 2, 3) VCC Standby Current Input Low Level Input High Level Voltage for Autoselect and Sector Protect Output Low Voltage Output High Level Low VCC Lock-Out Voltage VCC = 5.25 V IOL = 12 mA, VCC = VCC Min IOH = -2.5 mA, VCC = VCC Min 2.4 3.2 4.2 Test Description VIN = VSS to VCC, VCC = VCC Max VCC = VCC Max, A9 = 12.5 V VOUT = VSS to VCC, VCC = VCC Max CE# = VIL, OE# = VIH CE# = VIL, OE# = VIH VCC = VCC Max, CE# = VIH -0.5 2.0 10.5 20 30 0.4 Min Typ Max 1.0 50 1.0 30 40 1.0 0.8 VCC + 0.5 12.5 0.45 Unit A A A mA mA mA V V V V V V CMOS Compatible Parameter Symbol ILI ILIT ILO ICC1 ICC2 ICC3 VIL VIH VID VOL VOH1 VOH2 VLKO Low VCC Lock-out Voltage Parameter Description Input Load Current A9 Input Load Current Output Leakage Current VCC Active Read Current (Note 1) VCC Active Program/Erase Current (Notes 2, 3) VCC Standby Current (Note 4) Input Low Level Input High Level Voltage for Autoselect and Sector Protect Output Low Voltage Output High Voltage VCC = 5.25 V IOL = 12.0 mA, VCC = VCC Min IOH = -2.5 mA, VCC = VCC Min IOH = -100 A, VCC = VCC Min 0.85 VCC VCC -0.4 3.2 4.2 Test Description VIN = VSS to VCC, VCC = VCC Max VCC = VCC Max, A9 = 12.5 V VOUT = VSS to VCC, VCC = VCC Max CE# = VIL, OE# = VIH CE# = VIL, OE# = VIH VCC = VCC Max, CE# = VCC 0.5 V -0.5 0.7 x VCC 10.5 20 30 1 Min Typ Max 1.0 50 1.0 30 40 5 0.8 VCC + 0.3 12.5 0.45 Unit A A A mA mA A V V V V V V V Notes for DC Characteristics (both tables): 1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 6 MHz). The frequency component typically is less than 2 mA/MHz, with OE# at VIH. 2. ICC active while Embedded Algorithm (program or erase) is in progress. 3. Not 100% tested. 4. For CMOS mode only, ICC3 = 20 A max at extended temperatures (> +85C). 18 AM29F040B PRELIMINARY TEST CONDITIONS 5.0 V Table 6. Test Condition Test Specifications -55 All others Unit 1 TTL gate 30 5 0.0-3.0 1.5 1.5 100 20 0.45-2.4 0.8 2.0 pF ns V V V Device Under Test CL 6.2 k 2.7 k Output Load Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Note: Diodes are IN3064 or equivalent 21445B-12 Output timing measurement reference levels Figure 7. Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS Steady Changing from H to L Changing from L to H Don't Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) OUTPUTS KS000010-PAL AM29F040B 19 PRELIMINARY AC CHARACTERISTICS Read Only Operations Parameter Symbols JEDEC tAVAV tAVQV tELQV tGLQV Standard tRC tACC tCE tOE Description Read Cycle Time (Note 3) Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Read tOEH Output Enable Hold Time (Note 3) Toggle and Data# Polling CE# = VIL, OE# = VIL OE# = VIL Test Setup Min Max Max Max Min Min Max -55 55 55 55 30 0 10 18 18 Min 0 Speed Options (Note 1) -70 70 70 70 30 0 10 20 20 0 -90 90 90 90 35 0 10 20 20 0 -120 120 120 120 50 0 10 30 30 0 -150 150 150 150 55 0 10 35 35 0 Unit ns ns ns ns ns ns ns ns ns tEHQZ tGHQZ tAXQX tDF tDF tOH Chip Enable to Output High Z (Notes 2, 3) Output Enable to Output High Z (Notes 2, 3) Output Hold Time from Addresses, CE# or OE#, Whichever Occurs First Notes: 1. See Figure 7 and Table 6 for test conditions. 2. Output driver disable time. 3. Not 100% tested. tRC Addresses CE# tOE tOEH WE# HIGH Z Outputs Output Valid tCE tOH HIGH Z tDF Addresses Stable tACC OE# 0V 21445B-13 Figure 8. Read Operation Timings 20 AM29F040B PRELIMINARY AC CHARACTERISTICS Erase and Program Operations Parameter Symbols JEDEC tAVAV tAVWL tWLAX tDVWH tWHDX Std. tWC tAS tAH tDS tDH tOES tGHWL tELWL tWHEH tWLWH tWHWL tWHWH1 tWHWH2 tGHWL tCS tCH tWP tWPH tWHWH1 tWHWH2 tVCS Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Read Recover Time Before Write (OE# high to WE# low) CE# Setup Time CE# Hold Time Write Pulse Width Write Pulse Width High Byte Programming Operation (Note 2) Sector Erase Operation (Note 2) VCC Set Up Time (Note 1) Min Min Min Min Min Min Min Min Min Min Min Typ Typ Min 30 35 40 25 45 30 -55 55 Speed Options -70 70 -90 90 0 45 45 0 0 0 0 0 45 20 7 1 50 50 50 50 50 50 50 -120 120 -150 150 Unit ns ns ns ns ns ns ns ns ns ns ns s sec s Notes: 1. Not 100% tested. 2. See the "Erase And Programming Performance" section for more information. AM29F040B 21 PRELIMINARY Program Command Sequence (last two cycles) tAS tWC Addresses 555h PA tAH CE# tGHWL OE# tWP WE# tCS tDS Data tVCS VCC tDH PD tWPH Read Status Data (last two cycles) PA PA tCH tWHWH1 A0h Status DOUT Note: PA = program address, PD = program data, DOUT is the true data at the program address. 21445B-14 Figure 9. Program Operation Timings Erase Command Sequence (last two cycles) tWC Addresses 2AAh tAS SA 555h for chip erase Read Status Data VA tAH VA CE# tGHWL OE# tWP WE# tCS tDS tDH Data 55h 30h 10 for Chip Erase In Progress Complete tCH tWPH tWHWH2 tVCS VCC Note: SA = Sector Address. VA = Valid Address for reading status data. 21445B-15 Figure 10. Chip/Sector Erase Operation Timings 22 AM29F040B PRELIMINARY AC CHARACTERISTICS tRC Addresses VA tACC tCE CE# tCH OE# tOEH WE# tOH DQ7 High Z VA VA tOE tDF Complement Complement True Valid Data High Z DQ0-DQ6 Status Data Status Data True Valid Data Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle . 21445B-16 Figure 11. Data# Polling Timings (During Embedded Algorithms) tRC Addresses VA tACC tCE CE# tCH OE# tOEH WE# tOH DQ6/DQ2 High Z VA VA VA tOE tDF Valid Status (first read) Valid Status (second read) Valid Status (stops toggling) Valid Data Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. 21445B-17 Figure 12. Toggle Bit Timings (During Embedded Algorithms) AM29F040B 23 PRELIMINARY AC CHARACTERISTICS Enter Embedded Erasing WE# Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete Erase Suspend Read DQ6 DQ2 DQ2 and DQ6 toggle with OE# and CE# Note: Both DQ6 and DQ2 toggle with OE# or CE#. See the text on DQ6 and DQ2 in the "Write Operation Status" section for more information. 21445B-18 Figure 13. DQ2 vs. DQ6 AC CHARACTERISTICS Erase and Program Operations Alternate CE# Controlled Writes Parameter Symbols JEDEC tAVAV tAVEL tELAX tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1 tWHWH2 Standard tWC tAS tAH tDS tDH tGHEL tWS tWH tCP tCPH tWHWH1 tWHWH2 Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recover Time Before Write CE# Setup Time CE# Hold Time Write Pulse Width Write Pulse Width High Byte Programming Operation (Note 2) Sector Erase Operation (Note 2) Min Min Min Min Min Min Min Min Min Min Typ Typ 30 20 35 20 40 25 45 30 -55 55 Speed Options -70 70 -90 90 0 45 45 0 0 0 0 45 20 7 1 50 20 50 20 50 50 50 50 -120 120 -150 150 Unit ns ns ns ns ns ns ns ns ns ns s sec Notes: 1. Not 100% tested. 2. See the "Erase And Programming Performance" section for more information. 24 AM29F040B PRELIMINARY AC CHARACTERISTICS 555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase Data# Polling PA Addresses tWC tWH WE# tGHEL OE# tCP CE# tWS tCPH tDS tDH Data tRH A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase tAS tAH tWHWH1 or 2 tBUSY DQ7# DOUT Notes: 1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, DOUT = Array Data. 2. Figure indicates the last two bus cycles of the command sequence. 21445B-19 Figure 14. Alternate CE# Controlled Write Operation Timings ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Byte Programming Time Chip Programming Time (Note 3) Typ (Note 1) 1 8 7 3.6 Max (Note 2) 8 64 300 10.8 Unit sec sec s sec Comments Excludes 00h programming prior to erasure (Note 4) Excludes system-level overhead (Note 5) Notes: 1. Typical program and erase times assume the following conditions: 25C, 5.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90C, VCC = 4.5 V (4.75 V for -55), 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then does the device set DQ5 = 1. See the section on DQ5 for further information. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 4 for further information on command definitions. 6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles. AM29F040B 25 PRELIMINARY LATCHUP CHARACTERISTICS Min Input Voltage with respect to VSS on all I/O pins VCC Current -1.0 V -100 mA Max VCC + 1.0 V +100 mA Includes all pins except VCC. Test conditions: VCC = 5.0 V, one pin at a time. TSOP PIN CAPACITANCE Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ 6 8.5 7.5 Max 7.5 12 9 Unit pF pF pF Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25C, f = 1.0 MHz. PLCC AND PDIP PIN CAPACITANCE Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VPP = 0 Typ 4 8 8 Max 6 12 12 Unit pF pF pF Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25C, f = 1.0 MHz. DATA RETENTION Parameter Minimum Pattern Data Retention Time 125C 20 Years Test Conditions 150C Min 10 Unit Years 26 AM29F040B PRELIMINARY PHYSICAL DIMENSIONS PD 032 32-Pin Plastic DIP (measured in inches) 1.640 1.670 32 17 .530 .580 16 .045 .065 .140 .225 .005 MIN 0 10 .630 .700 .009 .015 .600 .625 Pin 1 I.D. SEATING PLANE .120 .160 .090 .110 .016 .022 .015 .060 16-038-S_AG PD 032 EC75 5-28-97 lv PL 032 32-Pin Plastic Leaded Chip Carrier (measured in inches) .485 .495 .009 .015 .125 .140 .080 .095 SEATING PLANE .400 REF. .013 .021 .026 .032 TOP VIEW .050 REF. .490 .530 .042 .056 .447 .453 .585 .595 .547 .553 Pin 1 I.D. SIDE VIEW 16-038FPO-5 PL 032 DA79 6-28-94 ae AM29F040B 27 PRELIMINARY PHYSICAL DIMENSIONS (continued) TS 032 32-Pin Standard Thin Small Package (measured in millimeters) 0.95 1.05 Pin 1 I.D. 1 7.90 8.10 0.50 BSC 18.30 18.50 19.80 20.20 0.08 0.20 0.10 0.21 0.05 0.15 1.20 MAX 0 5 0.50 0.70 16-038-TSOP-2 TS 032 DA95 3-25-97 lv 28 AM29F040B PRELIMINARY PHYSICAL DIMENSIONS (continued) TSR032 32-Pin Reversed Thin Small Outline Package (measured in millimeters) 0.95 1.05 Pin 1 I.D. 1 7.90 8.10 0.50 BSC 18.30 18.50 19.80 20.20 0.08 0.20 0.10 0.21 0.05 0.15 1.20 MAX 0 5 0.50 0.70 16-038-TSOP-2 TSR032 DA95 3-25-97 lv AM29F040B 29 PRELIMINARY REVISION SUMMARY FOR AM29F040B Global Formatted for consistency with other 5.0 volt-only data data sheets. Revision B+2 Distinctive Characteristics Changed minimum 100K write/erase cycles guaranteed to 1,000,000. Ordering Infomation Added extended temperature availability to the -55 and -70 speed options. AC Characteristics Revision B+1 AC Characteristics, Erase and Program Operations Added Note references to tWHWH1. Corrected the parameter symbol for VCC Set-up Time to tVCS; the specification is 50 s minimum. Deleted the last row in table. Erase/Program Operations; Erase and Program Operations Alternate CE# Controlled Writes: Corrected the notes reference for tWHWH1 and tWHWH2. These parameters are 100% tested. Corrected the note reference for tVCS. This parameter is not 100% tested. Erase and Programming Performance Changed minimum 100K program and erase cycles guaranteed to 1,000,000. Trademarks Copyright (c) 1998 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 30 AM29F040B |
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